Modeling Power Vertical High-k MOS Device With Interface Charges via Superposition Methodology-Breakdown Voltage and Specific ON-Resistance

被引：14
|
作者：
Wang, Zhigang [1 ]
Wang, Xi [1 ]
Kuo, James B. [2 ]
机构：
[1] Southwest Jiaotong Univ SWJTU, Sch Informat Sci & Technol, Chengdu 610000, Sichuan, Peoples R China
[2] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2018年 / 65卷 / 11期
基金：
中国国家自然科学基金;
关键词：
Analytical model; breakdown voltage (BV); interface charge; superjunction (SJ); high dielectric;
D O I：
10.1109/TED.2018.2870174
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An analytical model for the power vertical MOS device with a high-k insulating dielectric (HKMOS) is derived via the superposition methodology on the condition of punchthrough. Considering three portions-the superjunction part, the p-i-n diode, and the interface charges at the heterointerface based on the conservation of electric displacement, the HKMOS device could be modeled well as verified by the 2-D simulation results.
引用
收藏
页码：4947 / 4954
页数：8
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