A low-voltage CMOS LNA design utilizing the technique of capacitive feedback matching network

被引：0

作者：

Wu, Chung-Yu ^{[1
]}

Shahroury, Fadi Riad ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Inst Elect, Integrated Circuits & Syst Lab, Hsinchu 30039, Taiwan

来源：

2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3 | 2006年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a CMOS low noise amplifier (LNA) with a new input matching topology has been proposed, analyzed, and measured. The input matching network is designed through the technique of capacitive feedback matching network. The proposed LNA which is implemented in a 0.18-mu m 1P6M CMOS technology is operated at the frequency of 12.8 GHz. It has a gain S21 of 13.2 dB, a noise figure (NF) of 4.57 dB and an NFmin of 4.46 dB. The reverse isolation S12 of the LNA can achieve -40 dB and the input and output return losses are better than -11 dB. The input 1-dB compression point is -11 dBm. This LNA drains 10 mA from the supply voltage of 1 V.

引用

页码：78 / 81

页数：4

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