共 50 条
- [1] A Relaxed Bit-Write-Reducing and Error-Correcting Code for Non-Volatile Memories [J]. IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2018, E101A (07): : 1045 - 1052
- [2] Bit-Write-Reducing and Error-Correcting Code Generation by Clustering Error-Correcting Codewords for Non-Volatile Memories [J]. 2015 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 2015, : 682 - 689
- [3] A Write-Reducing and Error-Correcting Code Generation Method for Non-Volatile Memories [J]. 2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS), 2014, : 304 - 307
- [5] Compression Architecture for Bit-write Reduction in Non-volatile Memory Technologies [J]. 2014 IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES (NANOARCH), 2014, : 51 - 56
- [9] ERROR-CORRECTING CODES FOR COMPUTER MEMORIES [J]. AUTOMATION AND REMOTE CONTROL, 1991, 52 (05) : 595 - 627
- [10] On the bit error rate of repeated error-correcting codes [J]. 2014 48TH ANNUAL CONFERENCE ON INFORMATION SCIENCES AND SYSTEMS (CISS), 2014,