Power grid automatic metal filling algorithm forming maximum on-chip decoupling capacitance

被引：0

作者：

Tork, A. ^{[1
]}

AbulMakarem, M. ^{[1
]}

Dessouky, M. ^{[1
]}

机构：

[1] Mentor Graph Egypt, Cairo, Egypt

来源：

IDT 2007: SECOND INTERNATIONAL DESIGN AND TEST WORKSHOP, PROCEEDINGS | 2007年

关键词：

metal filling; decoupling capacitance; power grid; automatic power grid generation; simultaneous switching noise;

D O I：

暂无

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

With the extensive scaling in transistor sizes, more functionality has gone on single chip. Modern mixed signal chips designers face problems regarding the supply noise due to the simultaneous switching noise (SSN). SSN is enforced on power supply grid due to switching digital circuits. Supply SSN gas a deep impact on nearby analog circuits performance. The need for supply decoupling capacitance by analog circuits is essential. MOS Decoupling capacitance are prone to process and temperature variations. In this paper, we present an algorithm for generating power distribution grid with maximum parasitic capacitance for power supply decoupling using free metal layers. The automatically generated layout is DRC free. The algorithm has been tested on 0.13u generic process producing 6.01pF for bottom plate capacitance and 2.34pF for side wall capacitance with a total capacitance of 8.35pF on 0.5mm x 0.5mm of chip area.

引用

页码：157 / 159

页数：3

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