A Reconfigurable Baseband Processor For Wireless OFDM Synchronization Sub-System

被引：0

作者：

Abdelall, Mahmoud ^{[1
]}

Shalash, Ahmed F. ^{[1
]}

Fahmy, Hossam A. H. ^{[1
]}

机构：

[1] Cairo Univ, Fac Engn, Ctr Wireless Studies, Cairo, Egypt

来源：

2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2011年

关键词：

RECEIVER;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, an Application Specific Instruction-set Processor (ASIP) architecture to perform all OFDM synchronization tasks is proposed. While applicable to many OFDM systems, the proposed architecture is tested on Long Term Evolution (LTE Rel. 8) and WiMAX 802.16e systems. The synchronization tasks include, but not limited to symbol timing, fine carrier frequency offset (CFO) estimation, coarse CFO estimation, cell search, residual CFO estimation and sampling clock frequency offset estimation. The engine is scalable and runs at 120 MHz with a total gate count of 118k and control overhead less than 10% of total processing cycles. The results of software simulations as well as the results of verilog synthesis are presented.

引用

页码：2385 / 2388

页数：4

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