A Versatile Recognition Processor for Sensor Network Applications

被引：0
|
作者：
Takashima, Risako [1 ]
Hanai, Yuya [1 ]
Hori, Yuichi [1 ]
Kuroda, Tadahiro [1 ]
机构：
[1] Keio Univ, Tokyo 108, Japan
来源：
2010 15TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2010) | 2010年
关键词：
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
A versatile recognition processor is presented that comprises 2.1M transistors using a 90nm CMOS technology. It performs detection and recognition from image/video, sound and acceleration signals with energy consumption of sub-mJ/frame. The versatility and the power efficiency are attributed to optimal architecture design employing Haar-like Feature and Cascaded Classifier.
引用
收藏
页码：344 / 345
页数：2
相关论文
共 50 条
  • [1] ARCHITECTURE DESIGN OF VERSATILE RECOGNITION PROCESSOR FOR SENSORNET APPLICATIONS
    Hori, Yuichi
    Hanai, Yuya
    Nishimura, Jun
    Kuroda, Tadahiro
    [J]. IEEE MICRO, 2009, 29 (06) : 44 - 57
  • [2] A Versatile Body Sensor Network for Health Care Applications
    Kim, Saim
    Beckmann, Lisa
    Pistor, Moritz
    Cousin, Linda
    Walter, Marian
    Leonhardt, Steffen
    [J]. PROCEEDINGS OF THE 2009 FIFTH INTERNATIONAL CONFERENCE ON INTELLIGENT SENSORS, SENSOR NETWORKS AND INFORMATION PROCESSING, 2009, : 175 - 180
  • [3] A Versatile Body Sensor Network for Health Care Applications
    Kim, Saim
    Beckmann, Lisa
    Pistor, Moritz
    Cousin, Linda
    Walter, Marian
    Leonhardt, Steffen
    [J]. 2009 INTERNATIONAL CONFERENCE ON INTELLIGENT SENSORS, SENSOR NETWORKS AND INFORMATION PROCESSING (ISSNIP 2009), 2009, : 169 - 174
  • [4] Low power processor design for wireless sensor network applications
    Xu, YJ
    Liu, LY
    Shen, PF
    Lv, T
    Li, XW
    [J]. 2005 INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS, NETWORKING AND MOBILE COMPUTING PROCEEDINGS, VOLS 1 AND 2, 2005, : 921 - 924
  • [5] Exploring the processor and ISA design for wireless sensor network applications
    Mysore, Shashidhar
    Agrawal, Banit
    Chong, Frederic T.
    Sherwood, Timothy
    [J]. 21ST INTERNATIONAL CONFERENCE ON VLSI DESIGN: HELD JOINTLY WITH THE 7TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS, 2008, : 59 - 64
  • [6] VERSATILE VECTOR PROCESSOR FOR MULTICHANNEL SPEECH RECOGNITION
    OSBORN, RR
    [J]. JOURNAL OF THE ACOUSTICAL SOCIETY OF AMERICA, 1979, 65 : S132 - S132
  • [7] VERSATILE BUS SUITS REALTIME PROCESSOR APPLICATIONS
    FISCHER, W
    ROPER, P
    [J]. COMPUTER DESIGN, 1984, 23 (07): : 137 - &
  • [8] Optimization of Boundary Recognition Algorithms for Wireless Sensor Network Applications
    Simek, Milan
    Bocek, Jan
    Moravek, Patrik
    [J]. 2011 34TH INTERNATIONAL CONFERENCE ON TELECOMMUNICATIONS AND SIGNAL PROCESSING (TSP), 2011, : 189 - 194
  • [9] Versatile processor for GF(pm) arithmetic for use in cryptographic applications
    Byrne, A.
    Popovici, E.
    Marnane, W. P.
    [J]. IET COMPUTERS AND DIGITAL TECHNIQUES, 2008, 2 (04): : 253 - 264
  • [10] Versatile processor for GF(pm) arithmetic for use in cryptographic applications
    Byrne, A.
    Marnane, W. P.
    [J]. 24TH NORCHIP CONFERENCE, PROCEEDINGS, 2006, : 281 - +
12345