A resource balancing approach to SoC test scheduling

被引：0
|
作者：
Zhao, D [1 ]
Upadhyaya, S [1 ]
机构：
[1] SUNY Buffalo, Dept Comp Sci & Engn, Buffalo, NY 14260 USA
来源：
PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V: BIO-MEDICAL CIRCUITS & SYSTEMS, VLSI SYSTEMS & APPLICATIONS, NEURAL NETWORKS & SYSTEMS | 2003年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
We present a novel test scheduling algorithm for embedded core-based SoCs. We formulate the test scheduling as a shortest path problem with the feature of evenly balanced resource usage. Improvements to the basic algorithm are sought by core-grouping and all-permutation scheduling. We also extend the algorithm to allow multiple test sets selection to facilitate the testing for various fault models. A simulation study is performed to quantify the benefits of our new scheduling approach.
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收藏
页码：525 / 528
页数：4
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