HMFPCC: - Hybrid-Mode Floating Point Conversion Co-processor

This research and development on conversion co-processor presents an abstract-level hardware implementation of the conversion between various number formats for FPGAs in modular way. Replacing the floating point expressions with specialized integer or fixed point operations can greatly improve the system performance in several applications. The replacement requires several types of conversions from one format to another format. The proposed conversion co-processor accelerator can work in parallel with HOST machine to accept a large amount of input data and convert to another format and apply fixed point or integer arithmetic operations and the result is converted back to the floating point or fixed point format. The floating point conversions unit designs are fully compliant with the IEEE 7542008 standard. The proposed system has been tested on Xilinx Virtex 6 xc6vlx550t-2ff1759 FPGA and achieves a throughput of 350MFLOPs per second.