Design issues for flip-chip ICs in multilayer packages

被引：0
|
作者：
Frye, RC
机构：
来源：
TENTH ANNUAL IEEE INTERNATIONAL ASIC CONFERENCE AND EXHIBIT, PROCEEDINGS | 1997年
关键词：
D O I：
10.1109/ASIC.1997.617017
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Flip-chip area artery attachment, originally developed for MCMs, offers IC size reduction and improved operating speed, especially for high-end ASICs with large numbers of l/O. It is also proving to be well-suited for use in single-chip EGA packages. A key problem for most designers having limited experience with the technology, however is the lack of a widely accepted design methodology. This paper examines the advantages of the flip-chip structure, discusses emerging physical design methodologies and points out some of the remaining challenges in flip-chip ASIC design.
引用
收藏
页码：259 / 264
页数：6
相关论文
共 50 条
  • [1] Reliability issues for flip-chip packages
    Ho, PS
    Wang, GT
    Ding, M
    Zhao, JH
    Dai, X
    [J]. MICROELECTRONICS RELIABILITY, 2004, 44 (05) : 719 - 737
  • [2] A Circuit Edit Method for ICs of Flip-Chip/Multilayer Interconnected Structure
    Lin, Xiaoling
    Zhang, Xiaowen
    Gao, Rui
    [J]. Huanan Ligong Daxue Xuebao/Journal of South China University of Technology (Natural Science), 2020, 48 (12): : 63 - 71
  • [3] Design of ICs for flip-chip integration with optoelectronic device arrays
    Kiamilev, FE
    Krishnamoorthy, AV
    Rozier, RG
    Rieve, J
    Aplin, GF
    Hull, CD
    Farbarik, R
    Oettel, RE
    [J]. 1997 IEEE MULTI-CHIP MODULE CONFERENCE - PROCEEDINGS, 1997, : 163 - 167
  • [4] Reliability issues of low-cost overmolded flip-chip packages
    Lin, YM
    Liu, WN
    Guo, WF
    Shi, FG
    [J]. IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2005, 28 (01): : 79 - 88
  • [5] ENCAPSULANTS USED IN FLIP-CHIP PACKAGES
    SURYANARAYANA, D
    WU, TY
    VARCOE, JA
    [J]. IEEE TRANSACTIONS ON COMPONENTS HYBRIDS AND MANUFACTURING TECHNOLOGY, 1993, 16 (08): : 858 - 862
  • [6] Predictive model for optimized design parameters in flip-chip packages
    Park, SB
    Sammakia, B
    Raghunathan, K
    [J]. ITHERM 2004, VOL 2, 2004, : 458 - 464
  • [7] Flip-chip ICs SEE Testing Technique
    Bobrovsky, D. V.
    Pechenkin, A. A.
    Novikov, A. A.
    Chumakov, A. I.
    Ryasnoy, N. V.
    Churilin, Y. V.
    [J]. 2017 IEEE 30TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL), 2017, : 309 - 311
  • [8] Design of CMOS ICs for flip-chip integration with optoelectronic device arrays
    Chandramani, P
    Kiamilev, FE
    Krishnamoorthy, AV
    Rozier, RG
    Ekman, J
    Farbarik, R
    [J]. OPTOELETRONIC INTEGRATED CIRCUITS AND PACKAGING III, 1999, 3631 : 198 - 204
  • [9] Predictive model for optimized design parameters in flip-chip packages and assemblies
    Park, Seungbae
    Lee, H. C.
    Sammakia, Bahgat
    Raghunathan, Karthik
    [J]. IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, 2007, 30 (02): : 294 - 301
  • [10] An analysis of interface delamination in flip-chip packages
    Mercado, LL
    Sarihan, V
    Hauck, T
    [J]. 50TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 2000 PROCEEDINGS, 2000, : 1332 - 1337
12345