A resurfed high-voltage NMOS device fully compatible with a low-voltage 0.8 mu m BiCMOS technology

The design and implementation of a resurfed high-voltage NMOS device in a low-voltage 0.8 mu m BiCMOS technology is reported in this paper. Because of its full compatibility with existing technology, the high-voltage NMOS device can be fabricated with low-voltage circuitry on the same chip without requiring any additional processing steps. Two-dimensional process and device simulations were used to design the device. While shorter channel lengths are technologically feasible, 1.5 mu m was found to be the minimum drawn channel length to prevent channel punchthrough. Depending on the drift region length (2.8-16 mu m), breakdown voltages and specific on-resistances in the ranges of 70-124 V and 1.6-19 m Omega cm(2), respectively, were obtained on experimental test devices with a channel length of 1.5 mu m.