Adaptive Combined Macro and Micro-Exploration of Concurrent Applications mapped on shared Bus Reconfigurable SoC

This paper describes an adaptive system-level (macro) exploration method for heterogeneous Reconfigurable System-on-a-Chip (RSoC) systems with shared bus architectures. The proposed method starts by profiling computationally intensive tasks given in ANSI-C and by automatically partitioning them into SW and HW. Each HW partition is in turn explored using a High-Level Synthesis (HLS) design space explorer (DSE) (micro exploration) in order to obtain the smallest micro architecture for each latency within a given latency range. These exploration results are passed to the system-level explorer to obtain a system-level trade-off curve with unique area vs. performance trade-offs for different mappings and bus schedules. The designer can thus select the system within a given area and performance budget. The exploration method proposed includes a complete automatic partitioning, scheduling and exploration method, which takes as input multiple independent applications which will execute concurrently on the same heterogeneous system, given in ANSI-C. This work also introduces the concept of Control Offset (CO) as an input parameters to prune configurations' design space and thus allowing the control the Quality of Results (QoR) vs. the running time by setting a single parameter. Experimental results show that our proposed method is very efficient.