A single error correcting and double error detecting coding scheme for computer memory systems

被引：8

作者：

Lala, PK ^{[1
]}

机构：

[1] Univ Arkansas, Dept Comp Sci & Comp Engn, Fayetteville, AR 72701 USA

来源：

18TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS | 2003年

关键词：

D O I：

10.1109/DFTVS.2003.1250117

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes a new coding technique for single error correction and double error detection in computer memory systems. The number of 1's in the parity check matrix for the proposed coding is fewer than all currently available codes for this purpose. This results in simplified encoding and decoding circuitry for error detection and correction.

引用

页码：235 / 241

页数：7

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