Remotizing and Virtualizing Chips and Circuits for Hardware-based Capture-the-Flag Challenges

被引:1
|
作者
Roascio, Gianluca [1 ,2 ]
Cerini, Samuele Yves [2 ]
Prinetto, Paolo [1 ,2 ,3 ]
机构
[1] Politecn Torino, Turin, Italy
[2] CINI Cybersecur Natl Lab, Rome, Italy
[3] IMT Lucca, Lucca, Italy
关键词
cybersecurity; education; training; gamification; capture-the-flag; challenge; hardware; hardware security;
D O I
10.1109/EuroSPW55150.2022.00057
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
In the very rapid digital revolution we are experiencing, the availability of cybersecurity experts becomes critical in every organization and at multiple levels. However, classical and theory-oriented training seems to lack effectiveness and power of attraction, while professional selection and training processes based on cybersecurity gamification are being successfully experimented, among which Capture-the-Flag (CTF) competitions certainly stand out. Nevertheless, careful analysis reveals that such initiatives have a major shortcoming in addressing security issues when training people to tackle hardware-related security issues. Several motivations can be identified, including the inadequate technical knowledge of the White Teams charged of the challenges preparations, and the evident logistic problems posed by the availability of real hardware devices when the numbers of trainees significantly scales up. This paper presents a platform able to provide as a service hardware-based CTF challenges and exercises, involving circuits and chips that can be physically connected to a server or simulated, to deal with topics such as hardware bugs, flaws and backdoors, vulnerabilities in test infrastructures, and side-channel attacks. The platform is presented from a technical perspective, and data for deducting related efficiency, stability and scalability are offered.
引用
收藏
页码:477 / 485
页数:9
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    [J]. 2023 32ND ANNUAL CONFERENCE OF THE EUROPEAN ASSOCIATION FOR EDUCATION IN ELECTRICAL AND INFORMATION ENGINEERING, EAEEIE, 2023, : 156 - 161
  • [5] Hardware-based network management framework for monitoring and testing of system-on-chips
    Laouamri, O
    Aktouf, C
    [J]. CONTEL 2005: PROCEEDINGS OF THE 8TH INTERNATIONAL CONFERENCE ON TELECOMMUNICATIONS, VOLS 1 AND 2, 2005, : 141 - 146
  • [6] NBTI-Aware Design of Integrated Circuits: A Hardware-Based Approach
    Copetti, T.
    Cardoso Medeiros, G.
    Bolzani Poehls, L.
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    [J]. 2015 16TH LATIN-AMERICAN TEST SYMPOSIUM (LATS), 2015,
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