Real-time correction system for improving the disparity image

被引:0
|
作者
Song, Sunmin [1 ]
Lee, SangJun [1 ]
Jeon, Jae Wook [1 ]
机构
[1] Sungkyunkwan Univ, Sch Informat & Commun Engn, Suwon 400746, South Korea
关键词
FPGA; disparity image; post-processing; hardware architecture; verilog;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
A correction method for local stereo matching disparity images is an essential technology in stereo vision. We propose the hardware architecture for correcting a real-time disparity image. This method uses the similarity between the pixel of invalid disparity value and the neighboring pixels to estimate an alternative value for the invalid value. The experimental results showed that the proposed system can correct a disparity image in real time for 60fps image processing.
引用
收藏
页码:1138 / 1142
页数:5
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