A Low Power Fast Ethernet Physical Layer Transceiver

被引：0

作者：

Buhr, Simon ^{[1
]}

Xu, Xin ^{[1
]}

Kreissig, Martin ^{[1
]}

Ellinger, Frank ^{[1
]}

机构：

[1] Tech Univ Dresden, Chair Circuit Design & Network Theory, D-01062 Dresden, Germany

来源：

2019 26TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS) | 2019年

关键词：

Fast Ethernet; Low Power; Transceiver; Physical Layer;

D O I：

10.1109/icecs46596.2019.8964920

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work presents the design of a low power Fast Ethernet physical layer (PHY) transceiver. The PHY chip is implemented in a 180nm technology of GLOBALFOUNDRIES and optimized for lowest power consumption. Measurement results demonstrate error free data transmission with 100 Mb/s over up to 100m category 5 unshielded twisted pair cables. Under full link utilization using a 100m cable, the power consumption is only 70mW. This is, to the best of the authors knowledge, the lowest power consumption reported to date for such a Fast Ethernet PHY transceiver.

引用

页码：478 / 481

页数：4

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