A High-Resolution and Robust 12-bit DPWM for Digital DC-DC Converters

This paper presents the design and implementation of a supply and process-insensitive 12-bit Digital Pulse Width Modulator (DPWM) for digital DC-DC converters. The DPWM is realized by a ring oscillator-based segmented tapped delay line and a counter-comparator. The number of delay cells required is reduced by employing a proposed delay cell reuse technique. The ring oscillator of the tapped delay line is made insensitive to supply and process variation by biasing the differential delay cells with a supply-insensitive replica bias circuit. Simulation results show that the variation of the switching frequency of the DPWM at 1.02 MHz is 0.4% for supply voltage variation between 1.5 V and 2.5 V and 0.95% over the temperature range from -40 degrees C to 90 degrees C. Monte-Carlo simulation was also performed to account for the effect of mismatch between the transistors of the ring oscillator. The worst case delay of the delay cells is 0.87% for +/- 5% (3-sigma) mismatch. The design was fabricated in CMOS 0.18 mu m process and the fabricated DPWM achieved a supply sensitivity of 0.82% and a current consumption of 14 mu A.