Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array

被引：0

作者：

Kim, Jinseok ^{[1
]}

Koo, Jongeun ^{[1
]}

Kim, Taesu ^{[1
]}

Kim, Yulhwa ^{[1
]}

Kim, Hyungjun ^{[1
]}

Yoo, Seunghyun ^{[1
]}

Kim, Jae-Joon ^{[1
]}

机构：

[1] Pohang Univ Sci & Technol, Pohang, South Korea

来源：

2019 SYMPOSIUM ON VLSI CIRCUITS | 2019年

关键词：

D O I：

10.23919/vlsic.2019.8778160

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We introduce a SRAM-based binary neural network (BNN) hardware which uses a single 6T SRAM cell for XNOR operation for the first time. The cell is 45% smaller than the previous 8T bitcell for XNOR operation. We also propose an in-memory calibration and batch normalization to achieve more reliable operation under the presence of process variation.

引用

页码：C118 / C119

页数：2

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