Carbon Nanotube Bundles as Nanoscale Chip to Package Interconnects

被引：0
|
作者：
Chiariello, Andrea G. [1 ]
Miano, Giovanni [1 ]
Maffucci, Antonio [2 ]
机构：
[1] Univ Naples Federico II, Dipartimento Ingn Elettr, I-80125 Naples, Italy
[2] Univ Cassino, DAEIMI, I-03043 Cassino, Italy
来源：
2009 9TH IEEE CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO) | 2009年
关键词：
carbon nanotubes; nanopackaging;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The paper presents recent advances in carbon nanotube interconnect modeling, with focus on their application to nanoscale chip packaging. An enhanced electrical model of carbon nanotube bundles is used, able to take into account the effects of different nanotube sizes covered by this application. The use of carbon nanotubes as chip to package interconnects at nanoscale dimensions is analyzed and the electrical parasitics introduced by these interconnects are compared to those predicted by other packaging technologies.
引用
收藏
页码：58 / 61
页数：4
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