Performance analysis of ATM switches with multistage multipath packet switching interconnection networks

Because of their ability of nonblocking and fault tolerance, multistage-multipath networks provide very interesting and useful characteristics for ATM switches and large-scale parallel computers. In this paper, an analytical model for analysis of ATM switches based on multistage-multipath packet-switching interconnection networks with finite buffering capacity at the output of switching elements is presented. The proposed model is general in that it analyzed ATM switches under uniform and nonuniform traffic. The existing methods for analysis of ATM switches with single-path buffered interconnection networks, cannot be used to evaluate the performance of multipath networks. Firstly, in the paper, a general model of synchronous buffered switching element, using output buffering, under assumption of finite buffer size for a very general class of traffic patterns, is presented. It is assumed that the subsequent stages of the network are nearly independent and a model is extended for entire network under this assumption. Analytical results obtained with proposed model are then compared with the results obtained for single path networks, and it is shown that the model is general enough for the class of multipath networks.