A multi-lingual synthesis and verification environment

The adoption of hardware description languages as a design specification formalism, in the electronic design automation industry, has reached acceptance during the last years. This effort has been mainly supported by the VHDL and Verilog standardization activities, which are now offering a common formalism among different tool vendors, as well as novel ideas like the SystemC C++ class library, which promises hardware modeling using C++ syntax and a higher level of specification abstraction. The broad range of modern description language spectrum, supports efficient language based synthesis processes, starting at even higher abstraction levels, This paper presents a language based design environment, which combines synthesis and formal verification tasks, using an advanced compiler generator and based on language transformations. This combination, presenting low complexity, offers more power to language based synthesis and design management and can be used to find errors and better understand issues of behavioral modeling.