Ultralow-Latency Hardware-in-the-Loop Platform for Rapid Validation of Power Electronics Designs

被引：95
|
作者：
Majstorovic, Dusan [1 ,2 ]
Celanovic, Ivan [3 ]
Teslic, Nikola Dj. [1 ,2 ]
Celanovic, Nikola [1 ,4 ]
Katic, Vladimir A. [1 ]
机构：
[1] Univ Novi Sad, Fac Tech Sci, Novi Sad 21000, Serbia
[2] RT RK LLC, Novi Sad 21000, Serbia
[3] MIT, Boston, MA 02139 USA
[4] Typhoon RTDS, CH-5400 Baden, Switzerland
来源：
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS | 2011年 / 58卷 / 10期
关键词：
Automatic design verification; electronic design automation for power electronics (PE); field-programmable gate array (FPGA)-based ultralow-latency (ULL) processor; hardware in the loop (HIL); real-time digital simulator for PE and motor drives; TIME-DOMAIN SIMULATION; SYSTEMS; EMULATOR;
D O I：
10.1109/TIE.2011.2112318
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper introduces a unified approach to the validation of power-electronics (PE) control hardware, firmware, and software designs. It is based on a scalable application-specific ultralow-latency (ULL) digital processor core. The proposed ULL processor core simulates PE converters and systems comprising multiple power converters with a fixed 1-mu s simulation time step and latency, regardless of the size of the system. Owing to its ULL, the proposed platform enables the fully automatic testing and validation of the complete PE design comprising component safe-operating-area validation, system protection, firmware, and software implementation as well as overall system performance optimization.
引用
收藏
页码：4708 / 4716
页数：9
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