Joint equalization and coding for on-chip bus communication

被引：6

作者：

Sridhara, Srinivasa R. ^{[1
]}

Balamurugan, Ganesh ^{[2
]}

Shanbhag, Naresh R. ^{[3
,4
]}

机构：

[1] Univ Illinois, Urbana, IL 61801 USA

[2] Intel Corp, Circuits Res Lab, Hillsboro, OR 97124 USA

[3] Intel Corp, Coordinated Sci Lab, Hillsboro, OR 97124 USA

[4] Intel Corp, Dept Elect & Comp Engn, Hillsboro, OR 97124 USA

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2008年 / 16卷 / 03期

关键词：

coding; crosstalk avoidance; delay; equalization; interconnection networks; on-chip buses; system-on-chip (SOC);

D O I：

10.1109/TVLSI.2007.915484

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we propose using joint equalization and coding to improve on-chip communication speeds by signaling at rates beyond the rate governed by resistance-capacitance (RC) delay of the interconnect. Operating beyond the RC limit introduces inter-symbol interference (ISI). We mitigate the effects of ISI by employing equalization. The proposed equalizer employs a variable threshold inverter whose switching threshold is modified as a function of past output of the bus. We demonstrate even higher speedups by combining equalization with crosstalk avoidance coding. Specifically, simulation results for a 10-mm 32-bit bus in 0.13-mu m CMOS technology show that 1.28 X speedup is achievable by equalization alone and 2.30 X speedup is achievable by joint equalization and coding.

引用

页码：314 / 318

页数：5

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