A SAR-Assisted Continuous-Time Incremental ΣΔ ADC With First-Order Noise Coupling

被引：0
|
作者：
Hsieh, Yu-Lun [1 ]
Lee, Tai-Cheng [1 ]
机构：
[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei, Taiwan
来源：
2019 IEEE 13TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) | 2019年
关键词：
Incremental sigma-delta Sigma Delta ADC; continuous-time; successive-approximation-register (SAR); noise coupling (NC); excess-loop-delay compensation (ELDC);
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 25-kHz 3rd-order continuous-time incremental sigma-delta modulator is proposed by utilizing a 5-bit successive-approximation-register (SAR) quantizer, incorporating 1st-order noise coupling (NC) and excess-loopdelay compensation (ELDC) into the switched-capacitor (SC) SAR digital-to-analog converter (DAC). This prototype fabricated in a TSMC 40 nm LP CMOS technology measures a peak 71.98 dB SNDR at an over-sampling ratio (OSR) of 32, yielding a Schreier FoM of 160.5 dB and a Walden FoM of 1.39 pJ/conversion-step. The modulator occupies an active area smaller than 0.32 mm(2) and consumes 225 mu W.
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页数：4
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