Continuous-time sigma-delta modulators with reduced timing jitter sensitivity based on time delays

被引：11

作者：

Hernández, L ^{[1
]}

机构：

[1] Univ Carlos III Madrid, Dept Elect Technol, Madrid 28911, Spain

来源：

ELECTRONICS LETTERS | 2003年 / 39卷 / 14期

关键词：

D O I：

10.1049/el:20030609

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel continuous time sigma-delta modulator architecture is presented. This architecture employs a noise shaping filter based on time delays, which allows a high speed hardware implementation with transmission lines. This architecture is less sensitive to clock jitter and excess loop delay than the equivalent continuous time modulators based on integrators.

引用

页码：1039 / 1041

页数：3

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