Advanced design approaches for SFQ logic circuits based on the binary decision diagram

被引：2

作者：

Nishigai, T ^{[1
]}

Ito, M

Yoshikawa, N

Obata, K

Takagai, K

Takagai, N

Fujimaki, A

Terai, H

Yorozu, S

机构：

[1] Yokohama Natl Univ, Dept Elect & Comp Engn, Yokohama, Kanagawa 2408501, Japan

[2] Nagoya Univ, Dept Informat Engn, Nagoya, Aichi 4648603, Japan

[3] Nagoya Univ, Dept Quantum Engn, Nagoya, Aichi 4648603, Japan

[4] Natl Inst Commun Technol, Kobe, Hyogo 6542492, Japan

[5] ISTEC SRL, Tsukuba, Ibaraki 3058501, Japan

来源：

IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY | 2005年 / 15卷 / 02期

关键词：

adder; asynchronous circuit; BDD; binary decision diagram; dual rail; SFQ logic circuit; superconducting circuit;

D O I：

10.1109/TASC.2005.849855

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have been investigating a design methodology of SFQ logic circuits based on the binary decision diagram (BDD). In the previously proposed BDD SFQ logic circuits, we have used one-to-two binary switches as a node cell in a BDD tree. In this study we will propose a new implementation method of SFQ BDD circuits, in which two nodes are implemented aby using a 2-input 2-output switch gate. By employing the new approach, we have designed and implemented a one-bit full adder using the NEC 2.5 kA/cm(2) Nb standard process and the CONNECT cell library. The maximum operating frequency of the full adder was found to be 40 GHz by circuit simulations and 32.8 GHz by on-chip highspeed tests.

引用

页码：380 / 383

页数：4

共 50 条

[1] A new design approach for RSFQ logic circuits based on the binary decision diagram
Yoshikawa, N
Tago, H
Yoneyama, K
[J]. IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 1999, 9 (02) : 3161 - 3164
[2] Quantum-dot logic circuits based on the shared binary-decision diagram
Yamada, T
Kinoshita, Y
Kasai, S
Hasegawa, H
Amemiya, Y
[J]. JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 2001, 40 (07): : 4485 - 4488
[3] Quantum-dot logic circuits based on the shared binary-decision diagram
Yamada, Takashi
Kinoshita, Yoshitaka
Kasai, Seiya
Hasegawa, Hideki
Amemiya, Yoshihito
[J]. Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 2001, 40 (07): : 4485 - 4488
[4] A cell-based design approach for RSFQ circuits based on binary decision diagram
Koshiyama, J
Yoshikawa, N
[J]. IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2001, 11 (01) : 263 - 266
[5] Top-down RSFQ logic design based on a binary decision diagram
Yoshikawa, N
Koshiyama, J
[J]. IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2001, 11 (01) : 1098 - 1101
[6] Design and implementation of a high-speed bit-serial SFQ adder based on the binary decision diagram
Kawasaki, K
Yoda, K
Yoshikawa, N
Fujimaki, A
Terai, H
Yorozu, S
[J]. SUPERCONDUCTOR SCIENCE & TECHNOLOGY, 2003, 16 (12): : 1497 - 1502
[7] Design and demonstration of pipelined circuits using SFQ logic
Akahori, Akira
Sekiya, Akito
Yamada, Takahiro
Fujimaki, Akira
Hayakawa, Hisao
[J]. IEICE Transactions on Electronics, 2002, E85-C (03) : 641 - 644
[8] New logic circuits based on SFQ signals
Furuta, F
Suzuki, Y
Oya, E
Matsumoto, S
Akaike, H
Fujimaki, A
Hayakawa, H
Takai, Y
[J]. IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 1999, 9 (02) : 3553 - 3556
[9] Design and demonstration of pipelined circuits using SFQ logic
Akahori, A
Sekiya, A
Yamada, T
Fujimaki, A
Hayakawa, H
[J]. IEICE TRANSACTIONS ON ELECTRONICS, 2002, E85C (03): : 641 - 644
[10] Binary decision diagram to design balanced secure logic styles
Kim, Hyunmin
Hong, Seokhie
Preneel, Bart
Verbauwhede, Ingrid
[J]. 2016 IEEE 22ND INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS), 2016, : 239 - 244

← 1 2 3 4 5 →