Switching activity evaluation of CMOS digital circuits using logic timing simulation

被引：2

作者：

Juan-Chico, J

Bellido, MJ

Ruiz-de-Clavijo, P

Baena, C

Jiménez, CJ

Valencia, M

机构：

[1] Ctr Natl Microelect, Dept Diseno Digital, Inst Microelect Sevilla, Seville 41012, Spain

[2] Univ Seville, Dept Tecnol Elect, Seville, Spain

来源：

ELECTRONICS LETTERS | 2001年 / 37卷 / 09期

关键词：

Degradation delay model (DDM);

D O I：

10.1049/el:20010389

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The degradation delay model is applied to accurately estimate the switching activity in CMOS digital circuits. The model overcomes the limitations of conventional gate-level logic simulators to handle the propagation of glitches, a main sourer of switching activity. Model results of a four-bit multiplier are within 4% with respect to HSPICE. while Verilog overestimations are up to 68%.

引用

页码：555 / 557

页数：3

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