Exploiting locality in program graphs

The success of multithreaded systems depends on how quickly context switching between threads can be achieved. A fast context switch is only possible if threads are resident in fast but small memories. This limits, however, the number of active threads and thus the amount of latency that can be tolerated. The generality of dataflow makes it difficult to fetch and execute a sequence of logically related threads through the processor pipeline, thereby removing any opportunity to use registers across thread boundaries. Relegating the responsibilities of scheduling and storage management to the compiler alleviates this problem to some extent. In conventional architectures, the reduction in memory latency is achieved by providing (explicit) programmable registers and (implicit) high-speed caches. Amalgamating the idea of caches or register-caches within the dataflow framework can result in a higher exploitation of parallelism and hardware utilization. This paper investigates the suitability of cache memory in a dataflow paradigm. We present two heuristic schemes that allow the detection, exploitation, and enhancement of temporal and spatial localities in a dataflow graph (dataflow program). Dataflow graphs are partitioned into sub-graphs while preserving localities, and sub-graphs are distributed among the processors in order to reduce cache misses and communication cost. Simulation results showing the performance of the partitioning algorithms are presented and analyzed.