Implementation of Turbo Decoder Using MAX-LOG-MAP Algorithm in VHDL

被引：0
|
作者：
Mishra, Shivshankar [1 ]
Shukla, Harshit [2 ]
Madhekar, Suneel [1 ]
机构：
[1] DRDO, Res Ctr Imarat, PGAD, Hyderabad 50058, Andhra Pradesh, India
[2] PDPM IIITDM, Elect & Commun Engn Dept, Jabalpur 482005, India
来源：
2015 ANNUAL IEEE INDIA CONFERENCE (INDICON) | 2015年
关键词：
Error correcting codes; Turbo codes; iterative decoding; FPGA; MAX-LOG-MAP algorithm; INTERLEAVER DESIGN; CODES;
D O I：
暂无
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
Design and implementation of a Turbo decoder on FPGA is a challenging task. Various algorithms based on the BCJR algorithm have been proposed to enable the implementation of Turbo decoding in a hardware device. With the advent of FPGAs, the realization of the BCJR algorithm and different simplified versions of BCJR algorithm on hardware is possible. A VHDL implementation of Turbo decoder using the MAX-LOG-MAP algorithm has been discussed in this paper. The target device used for this implementation is Xilinx Virtex-6 FPGA. Simulation and synthesis were carried out using ModelSim SE 6.1 and Xilinx ISE 10.1. BER plots and input and output waveforms for interleaver, deinterleaver, MAX-LOG-MAP decoder and Turbo decoder are also presented.
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页数：6
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