Hybrid multiplierless FIR filter architecture based on NEDA

被引：0

作者：

Tecpanecatl-Xihuitl, J. Luis ^{[1
]}

Aguilar-Ponce, Ruth M. ^{[1
]}

Bayoumi, Magdy ^{[1
]}

机构：

[1] Univ SW Louisiana, Ctr Adv Comp Studies, Lafayette, LA 70504 USA

来源：

VLSI-SOC 2007: PROCEEDINGS OF THE 2007 IFIP WG 10.5 INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION | 2007年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents new hybrid multiplierless finite impulse response (FIR) architecture based on New Distributed Arithmetic (NEDA). The hybrid structure is a trade off between direct form and transposed direct form that results in a reduction of the critical path and the size of the delays elements as well as the fan-out. While the multiplications involved in the hybrid structure are replaced by a butterfly adder tree. Compared with previous methods, our proposed architecture achieves an average of 20% less additions. Moreover, the design method is simple and achieves better results than previous methods.

引用

页码：316 / 319

页数：4

共 50 条

[1] MULTIPLIERLESS FIR FILTER DESIGN USING GLOBAL VALUED NUMBERING AND ARCHITECTURE
Krishnan, Rejisha
Vijayakumar, S.
[J]. 2014 INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION AND NETWORKING TECHNOLOGIES (ICCCNT, 2014,
[2] On a multiplierless fir decenution filter design
Dolecek, Gordana Jovanovic
Nagrale, Naina Rao
[J]. 2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-4, 2007, : 967 - 970
[3] Multiplierless FIR filter design algorithms
Macleod, MD
Dempster, AG
[J]. IEEE SIGNAL PROCESSING LETTERS, 2005, 12 (03) : 186 - 189
[4] Optimal design of multiplierless FIR filter
Fang, J
Yi, T
Hong, ZL
[J]. 2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2003, : 848 - 851
[5] Review of Multiplierless Fir Filter Design Based On Graph Based Optimization
Ramamoorthy, Prabhu
Nallasamy, Viswanathan
[J]. 2018 CONFERENCE ON EMERGING DEVICES AND SMART SYSTEMS (ICEDSS), 2018, : 273 - 276
[6] NEDA Based Hybrid Architecture for DCT - HWT
Chandran, Vidhya
Mamatha, I
Tripathi, Shikha
[J]. 2016 INTERNATIONAL CONFERENCE ON VLSI SYSTEMS, ARCHITECTURES, TECHNOLOGY AND APPLICATIONS (VLSI-SATA), 2016,
[7] Optimization Design Approach for Multiplierless FIR Filter
Ranjithkumar, S.
Thilagam, S.
[J]. PROCEEDINGS OF 2016 ONLINE INTERNATIONAL CONFERENCE ON GREEN ENGINEERING AND TECHNOLOGIES (IC-GET), 2016,
[8] FPGA Realisation of Multiplierless FIR Filter Architectures
Pari, Britto J.
Rani, Joy Vasantha S. P.
Soundarya, A. Selestin
Vineeth, B.
Vijayakumar, P.
[J]. 2015 3rd International Conference on Signal Processing, Communication and Networking (ICSCN), 2015,
[9] A hybrid pipelined and multiplexed FIR filter architecture
Akram, W
Swartzlander, EE
[J]. ADVANCED SIGNAL PROCESSING ALGORITHMS, ARCHITECTURES, AND IMPLEMENTATIONS X, 2000, 4116 : 311 - 321
[10] Efficient Design and Implementation of Multiplierless FIR Filter
Dangra, Komal H.
Gawande, G. S.
[J]. 2016 INTERNATIONAL CONFERENCE ON COMPUTING COMMUNICATION CONTROL AND AUTOMATION (ICCUBEA), 2016,

← 1 2 3 4 5 →