Fast-Transient-Response Low-Voltage Integrated, Interleaved DC-DC Converter for Implantable Devices

A new self-start-up switched-capacitor charge pump is proposed for low-power, low-voltage and battery-less implantable applications. To minimize output voltage ripple and improve transient response, interleaving regulation technique is applied to a multi-stage Cross-Coupled Charge Pump (CCCP) circuit. It splits the power flow in a time-sequenced manner. Three cases of study are designed and investigated with body-biasing technique by auxiliary transistors: Four-stage Two-Branch CCCP (TBCCCP), the two-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP2) and four-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP4). Multi-phase nonoverlap clock generator circuit with body-biasing technique is also proposed which can operate at voltages as low as CCCP circuits. The proposed circuits are designed with input voltage as low as 300 to 400 mV and 20 MHz clock frequency for 1 pF load capacitance. Among the three designs, ITBCCCP4 has the lowest ramp-up time (41.6% faster), output voltage ripple (29% less) and power consumption (19% less). The Figure-Of-Merit (FOM) of ITBCCCP4 is the highest value among two others. For 400 mV input voltage, ITBCCCP4 has a 98.3% pumping efficiency within 11.6 mu s, while having a maximum voltage ripple of 0.1% and a power consumption as low as 2.7 nW. The FOM is 0.66 for this circuit. The designed circuits are implemented in 180-nm standard CMOS technology with an effective chip area of 84 x 89.4 pm for TBCCCP, 76.6 x 157.5 mu m for ITBCCCP2 and 134.5 x 142.9 mu m for ITBCCCP4.