New and efficient decoding architecture for Quasi-Cyclic LDPC codes

In this paper, a new and efficient decoding architecture, Single-Scan Layer Decoding (SLD), is realized in FPGA for multi-rate Quasi-Cyclic LDPC (QC-LDPC) codes. The SLD algorithm simplifies the nodes updating process and messages storing process of the offset min-sum algorithm, speeding up the decoding process and reducing nearly a half of resources consumption. Besides, the SLD algorithm, introducing the semi-parallel architecture into decoding architecture, can increase the convergence rate by 2X and decrease the interconnect complexity of hardware implementation. For multi-rate QC-LDPC Codes in 802.11.n, comparing with float-point software implementation, the degradations of the fixed-point SLD algorithm with 10 iterations in FPGA are all less than 0.1dB and the throughput of different code rates are all above 100Mbps.