Parallel Elite Genetic Algorithm for Test Scheduling of SoC

被引：0
|
作者：
Liu, Guangyu [1 ]
机构：
[1] Peking Univ, Shenzhen Grad Sch, Sch Elect & Comp Engn, Shenzhen, Peoples R China
来源：
PROCEEDINGS OF THE 2014 9TH IEEE CONFERENCE ON INDUSTRIAL ELECTRONICS AND APPLICATIONS (ICIEA) | 2014年
关键词：
SoC testing; test scheduling; parallel elite genetic algorithm;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Test scheduling is an important issue for testing the SoC (system-on-chip). This work uses a parallel elite genetic algorithm for test scheduling to reduce the test application time under the peak power constraint. It is applied to the 2D SoC and experimental results on benchmark circuits show that it is one of the most effective algorithms in solving the problem.
引用
收藏
页码：1985 / 1988
页数：4
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