Hardware Behavioural Modelling, Verification and Synthesis with UML 2.x Activity Diagrams

被引：16
|
作者：
Grobelny, Michal [1 ]
Grobelna, Iwona [1 ]
Adamski, Marian [1 ]
机构：
[1] Univ Zielona Gora, PL-65246 Zielona Gora, Poland
来源：
11TH IFAC/IEEE INTERNATIONAL CONFERENCE ON PROGRAMMABLE DEVICES AND EMBEDDED SYSTEMS (PDES 2012) | 2012年
关键词：
control system design; UML activity diagrams; control interpreted petri nets; formal verification; control system synthesis;
D O I：
10.3182/20120523-3-CZ-3015.00028
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
Modelling of hardware behavior is the fundamental process of hardware design project. Possible specification techniques, like UML 2.x Activity Diagrams or Control Interpreted Petri Nets, all have its advantages and disadvantages. Combing the accessibility of UML and full support for formal verification of Petri nets may significantly improve design quality. The article propose a system supporting logic controllers development, starting from a specification, going through formal verification (including model checking), and ending with synthesis.
引用
收藏
页码：134 / 139
页数：6
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