Performance analysis of the sliding-window parallel packet switch

This paper is concerned with performance analysis of the parallel packet switch (PPS) with sliding window (SW) scheme. The PPS is composed of multiple packet switches operating independently and in parallel. The traditional PPS dispatch algorithm uses round-robin (RR) [1][3]. The class of PPS is characterized by the deployment of parallel center-stage switches that all memory buffers run slower than the external line rate. In this paper, we propose a new SW packet switching scheme for the PPS, called SW-PPS. The SW-PPS can operate in a pipeline fashion to achieve overall switching operation. Under Bernoulli data traffic, the SW-PPS provides significantly higher performance when compared with RR-PPS. This paper presents a mathematical analytical model for RR-PPS and SW-PPS.