Property specification and static verification of UML models

被引：12
|
作者：
Siveroni, Igor [1 ]
Zisman, Andrea [1 ]
Spanoudakis, George [1 ]
机构：
[1] City Univ London, Dept Comp, London EC1V 0HB, England
来源：
ARES 2008: PROCEEDINGS OF THE THIRD INTERNATIONAL CONFERENCE ON AVAILABILITY, SECURITY AND RELIABILITY | 2008年
关键词：
D O I：
10.1109/ARES.2008.194
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
We present a Static Verification Tool (SVT), a system that performs static verification on UML models composed of UML class and state machine diagrams. Additionally. the SVT allows the user to add extra behavior specification in the form of guards and effects by defining a small action language. UML models are checked against properties written in a special-purpose property language that allows the user to specify linear temporal logic formulas that explicitly reason about UML components. Thus, the SVT provides a strong foundation for the design of reliable systems and a step towards model-driven security.
引用
收藏
页码：96 / +
页数：2
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