Single chip implementation of motion estimator dedicated to MPEG2 MP @ HL

被引：0
|
作者：
Onoye, T
Fujita, G
Takatsu, M
Shirakawa, I
Yamai, N
机构：
[1] Osaka Univ, Suita-shi, Japan
来源：
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | 1996年 / E79A卷 / 08期
关键词：
MPEG2; HDTV; VLSI; motion estimation;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A single chip motion estimator is described dedicatedly for MPEG2 MP @ HL moving pictures. Adopting a two-leveI hierarchical searching algorithm in detecting motion vectors, the computational labor can be reduced by 1/70 in comparison with the conventional algorithm. A novel mechanism is introduced into the full-search procedure, which attempts the maximum possible reuse of reference pixels in order to reduce the bandwidth of the frame memory interface. The proposed motion estimator is integrated in a 0.6 mu m triple-metal CMOS chip, which contains 1,450 K transistors on a 12.7 x 13.7 mm(2) die. The input clock rate can be attained up to 133 MHz, which enables the real time motion estimation for MPEG2 MP @ HL.
引用
收藏
页码：1210 / 1216
页数：7
相关论文
共 50 条
  • [1] VLSI implementation of hierarchical motion estimator for MPEG2 MP@HL
    Onoye, T
    Fujita, G
    Shirakawa, I
    Matsumura, K
    Ariyoshi, H
    Tsukiyama, S
    [J]. PROCEEDINGS OF THE IEEE 1996 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 1996, : 351 - 354
  • [2] Implementation of half-pel precision motion estimator for MPEG2 MP@HL
    Fujita, G
    Onoye, T
    Shirakawa, I
    Tsukiyama, S
    Matsumura, K
    [J]. 1996 IEEE TENCON - DIGITAL SIGNAL PROCESSING APPLICATIONS PROCEEDINGS, VOLS 1 AND 2, 1996, : 949 - 954
  • [3] Low-power motion estimator dedicated to MPEG2 MP@ML
    [J]. Zhang, W.J., 2001, Chinese Institute of Electronics (29):
  • [4] A VLSI architecture for MPEG2 MP@HL real time motion estimator
    Onoye, T
    Fujita, G
    Shirakawa, I
    Matsumura, K
    Ariyoshi, H
    Tsukiyama, S
    [J]. ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 2, 1996, : 664 - 667
  • [5] A single-chip MPEG2 MP@HL decoder for DTV recording/playback systems
    Watanabe, Y
    Otobe, Y
    Yoshitomi, K
    Takahashi, H
    Kohiyana, K
    [J]. IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, 2001, 47 (03) : 405 - 411
  • [6] A single-chip MPEG2 MP@HL decoder for DTV recording/playback system
    Watanabe, Y
    Otobe, Y
    Yoshitomi, K
    Takahashi, H
    Kohiyama, K
    [J]. ICCE: 2001 INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS, DIGEST OF TECHNICAL PAPERS, 2001, : 90 - 91
  • [7] Single-chip MPEG2 MP@HL decoder with multi-decode and seamless display features
    Takahashi, H
    Otobe, Y
    Kohiyama, K
    [J]. FUJITSU SCIENTIFIC & TECHNICAL JOURNAL, 2000, 36 (01): : 48 - 55
  • [8] Single chip implementation of MPEG2 decoder for HDTV level pictures
    Osaka Univ, Suita-shi, Japan
    [J]. IEICE Trans Fund Electron Commun Comput Sci, 3 (330-338):
  • [9] Single chip implementation of MPEG2 decoder for HDTV level pictures
    Onoye, T
    Masaki, T
    Morimoto, Y
    Sato, Y
    Shirakawa, I
    Matsumura, K
    [J]. IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 1996, E79A (03) : 330 - 338
  • [10] A high-performance memory storage architecture for MP@HL MPEG2 decoder chip
    Wu, Zhihua
    Luo, Rong
    Wang, Hui
    Yang, Huazhong
    [J]. ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2007, : 721 - 724
12345