Delay optimization and energy estimation in CMOS differential cascade voltage switch logic circuits

被引：0
|
作者：
Shams, M [1 ]
Elmasry, M [1 ]
机构：
[1] Univ Waterloo, VLSI Res Grp, Waterloo, ON N2L 3G1, Canada
来源：
ICM 2000: PROCEEDINGS OF THE 12TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS | 2000年
关键词：
D O I：
10.1109/ICM.2000.916416
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents closed-form expressions for delay optimization in,:MOS DCVSL circuits. It also introduces a method of estimating the delay and energy in such circuits. The results reported in this paper based on our technique are in good agreement kith HSPICE simulation results.
引用
收藏
页码：65 / 68
页数：4
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