Fast integer linear programming based models for VLSI global routing

Global routing is an essential part of VLSI physical design, and has been traditionally solved using sequential or concurrent methods. In the sequential techniques, routes are generated one at a time based on a predetermined ordering. These methods are very fast, but because of their sequential nature can result in sub-optimal solutions. The concurrent techniques attempt to solve the problem using global optimization techniques. These methods can provide a global view of the circuit's routing, but take a considerable amount of time. In this paper, a global router based on the concurrent techniques is presented. The proposed technique formulates the global routing problem as an integer linear programming (ILP) problem. This model combines the traditional wire length minimization model with the channel capacity minimization to obtain more accurate routings. In addition, the characteristics of the trees generated by our global router are investigated. A tree pruning technique based on the characteristics of the trees is developed to reduce the sizes of the MP problem, and consequently reduce the solution time. The results show an average of 58% improvement in solving time without any loss in the quality of the results.