Ethernet-Based Avionic Databus and Time-Space Partition Switch Design

被引:3
|
作者
Li, Jian [1 ]
Yao, Jianguo [1 ]
Huang, Dongshan [2 ]
机构
[1] Shanghai Jiao Tong Univ, Sch Software, Shanghai 200030, Peoples R China
[2] China Aeronaut Radio Elect Res Inst, Shanghai, Peoples R China
基金
中国国家自然科学基金;
关键词
Avionic data networks; avionics full-duplex switched ethernet (AFDX); real-time networking; shared memory switch; time-space partition; ATM SWITCH; PERFORMANCE; ARCHITECTURES; TECHNOLOGY; MANAGEMENT; NETWORK;
D O I
10.1109/JCN.2015.000051
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Avionic databuses fulfill a critical function in the connection and communication of aircraft components and functions such as flight-control, navigation, and monitoring. Ethernet-based avionic databuses have become the mainstream for large aircraft owning to their advantages of full-duplex communication with high bandwidth, low latency, low packet-loss, and low cost. As a new generation aviation network communication standard, avionics full-duplex switched ethernet (AFDX) adopted concepts from the telecom standard, asynchronous transfer mode (ATM). In this technology, the switches are the key devices influencing the overall performance. This paper reviews the avionic databus with emphasis on the switch architecture classifications. Based on a comparison, analysis, and discussion of the different switch architectures, we propose a new avionic switch design based on a time-division switch fabric for high flexibility and scalability. This also merges the design concept of space-partition switch fabric to achieve reliability and predictability. The new switch architecture, called space partitioned shared memory switch (SPSMS), isolates the memory space for each output port. This can reduce the competition for resources and avoid conflicts, decrease the packet forwarding latency through the switch, and reduce the packet loss rate. A simulation of the architecture with optimized network engineering tools (OPNET) confirms the efficiency and significant performance improvement over a classic shared memory switch, in terms of overall packet latency, queuing delay, and queue size.
引用
收藏
页码:286 / 295
页数:10
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