Accurate in-resolution level overlay metrology for multi patterning lithography techniques

Multi patterning lithography (MPL) breaks the k(1)=0.25 barrier to become the main candidate for 32nm device fabrication before 2010. When using MPL, overlay (OVL) becomes an essential part of the overall critical dimension (CD) budget and therefore can no longer be treated as a separate process control measure. Furthermore, the CD measured at each of the two consecutive lithography steps must be combined into one single 32nm process control measure and will require further improvements of CD-SEM precision, resolution and accuracy. The metrology challenges involved in measuring double patterning CD and OVL arise from the fact that across chip pitch variations (ACPV) are determined by the two separate lithographic processes [I]. This aspect makes the control of the process significantly more complex and requires careful measurement of the processes, both individually as well as combined. Meeting the ITRS specifications for CD and localized OVL measurements beyond 32nm half pitch is challenging and will require innovative CDSEM algorithmic solutions. This paper is a follow-up from last year's paper that introduced SEM metrology for MPL technology. In this paper, we report on the actual implementation of combined CD and OVL metrology solutions for the latest immersion scanner generation. We will describe the latest OVL measurements performed at ASML and demonstrate the robustness of the novel algorithm for accurate separation and recombination of two individual CD populations related to the consecutive MPL steps.