Development of low stress no-flow underfill for flip-chip application

被引:0
|
作者
Suzuki, O [1 ]
Kawamoto, S [1 ]
机构
[1] NAMICS CORP, Niigata 9503131, Japan
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
No-Flow Underfill (NUF) technology has been studied in the various ways about cure properties, self fluxing performance, and filler loading. Due to the filler entrapment between solder bump and contact pad on board, no-flow underfills are mostly no filler loading or filled with very low filler loading. The high coefficient of thermal expansion (CTE) of the polymer material has significantly lowered the reliability of flip chip assembly using NUF, and has limited its application to large chip assemblies. However, high-end flip-chip packages are heading towards a high pin count and large chip size with lead free issue and low-k's. [1] It is expected to develop a low stress underfill because of flip-chip such as low-k chip package has a brittle structure. This paper presents a novel approach to develop for low stress NUR We have realized flip-chip bonding with a high filler loading of NUF using a local reflow flip-chip bonding assembly process. We have evaluated a deformation of flip-chip package using Shadow Moire Technique during 260 reflow. This technique is one of the warpage measurement techniques that use a shadow of grating glass. Warpage of IC is decreasing during the reflow process after cooling it recovers initial warpage level. The effects of resin, filler size, filler loading level, fillet size is investigated Filler size, loading level, and fillet size is roughly the same result as reference. As a result, NUF is optimized for lead free soldering process with low stress.
引用
收藏
页码:185 / 189
页数:5
相关论文
共 50 条
  • [1] Incorporation of inorganic filler into the no-flow underfill material for flip-chip application
    Fan, LH
    Shi, SH
    Wong, CP
    [J]. INTERNATIONAL SYMPOSIUM ON ADVANCED PACKAGING MATERIALS: PROCESSES, PROPERTIES AND INTERFACES, PROCEEDINGS, 2000, : 303 - 310
  • [2] Simulation of no-flow underfill process for flip-chip assembly
    Kolbeck, A
    Hauck, T
    Jendrny, J
    Hahn, O
    Lang, S
    [J]. THERMAL AND MECHANICAL SIMULATION AND EXPERIMENTS IN MICROELECTRONICS AND MICROSYSTEMS, 2004, : 587 - 592
  • [3] Development of no-flow underfill for lead-free bumped flip-chip assemblies
    Zhang, ZQ
    Wong, CP
    [J]. PROCEEDINGS OF 3RD ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, 2000, : 234 - 240
  • [4] Development of no-flow underfill for lead-free bumped flip-chip assemblies
    Zhang, ZQ
    Wong, CP
    [J]. PROCEEDINGS OF INTERNATIONAL SYMPOSIUM ON ELECTRONIC MATERIALS AND PACKAGING, 2000, : 297 - 303
  • [5] Thermal characterization of a no-flow underfill material for flip-chip applications
    He, Y
    [J]. ABSTRACTS OF PAPERS OF THE AMERICAN CHEMICAL SOCIETY, 2005, 229 : U1112 - U1113
  • [6] Modeling of the curing kinetics of no-flow underfill in flip-chip applications
    Zhang, ZQ
    Wong, CP
    [J]. IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, 2004, 27 (02): : 383 - 390
  • [7] Thermomechanical and viscoelastic behavior of a no-flow underfill material for flip-chip applications
    He, Y
    [J]. THERMOCHIMICA ACTA, 2005, 439 (1-2) : 127 - 134
  • [8] Numerical simulation of conventional capillary flow and no-flow underfill in flip-chip packaging
    Hashimoto, Tomohisa
    Shin-Ichiro, Tanifuji
    Morinishi, Koji
    Satofuka, Nobuyuki
    [J]. COMPUTERS & FLUIDS, 2008, 37 (05) : 520 - 523
  • [9] Double-layer no-flow underfill process for flip-chip applications
    Zhang, ZQ
    Lu, JC
    Wong, CP
    [J]. IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, 2003, 26 (01): : 239 - 244
  • [10] The effect of toughening of no-flow underfill on fillet cracking of flip-chip device
    Moon, KS
    Fan, LH
    Wong, CP
    [J]. INTERNATIONAL SYMPOSIUM ON ADVANCED PACKAGING MATERIALS: PROCESSES, PROPERTIES AND INTERFACES, PROCEEDINGS, 2001, : 333 - 340