A high-performance multi-match priority encoder for TCAM-based packet classifiers

This paper introduces a high-speed and low power multi-match priority encoder design applicable in many computer and networking systems. We propose a scalable multi-match prioritizer logic circuitry that can successively find all or the first r matched inputs in a set. The design is well suited for multi-match packet classification tasks that utilize content addressable memories as the search engine. We use a data partitioning scheme to efficiently reorganize input data for further performance improvement. A VLSI implementation of our design in 0.18 mu m technology can achieve speed that outperforms the conventional multi-match packet classifier design by more than an order of magnitude. Overall power consumption is reduced by more than 40% using innovative partitioning which limits the search to a small portion of TCAM cells.