A Direct Observation of the Distributions of Local Trapped-Charges and the Interface-States near the Drain Region of the Silicon-Oxide-Nitride-Oxide-Silicon Device for Reliable Four-Bit/Cell Operations

被引：7

作者：

An, Ho-Myoung ^{[1
]}

Zhang, Yongjie ^{[1
]}

Kim, Hee-Dong ^{[1
]}

Seo, Yu Jeong ^{[1
]}

Kim, Byungcheul ^{[2
]}

Kim, Joo-Yeon ^{[3
]}

Kim, Tae Geun ^{[1
]}

机构：

[1] Korea Univ, Sch Elect Engn, Seoul 136701, South Korea

[2] Jinju Natl Univ, Dept Elect Engn, Jinju 660758, South Korea

[3] Ulsan Coll, Sch Elect Engn, Ulsan 680749, South Korea

来源：

JAPANESE JOURNAL OF APPLIED PHYSICS | 2010年 / 49卷 / 11期

关键词：

FLASH MEMORY; 2-BIT; NROM;

D O I：

10.1143/JJAP.49.114203

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

This paper reports the direct observation of the threshold voltage shifts with trapped charge densities as well as the interface state densities after 10(4) program/erase (P/E) cycles at each state of the four levels in the drain edge of the silicon-oxide-nitride-oxide-silicon (SONOS) structure We prepared a SONOS device with a 34 nm thick tunnel oxide showing 2 bit and 4 level operations at program voltages of 476 V with 10 year retention and 10(4) P/E endurance properties Then by using charge pumping methods we observed the vertical and the lateral distributions of the trapped charges and their interface states with the gate biases at each level of the four states in the drain edge The trapped charges densities at the 10 01 and '00 states in the drain region were estimated to be 1 4 x 10(12) 30 x 10(12) and 49 x 10(12) cm(-2) respectively with a lateral width of 220 nm The peak location of the interface state density was shifted from the drain edge to the channel with an increase in the gate bias These observations will be quite useful to optimize the program conditions for reliable 4 bit/cell SONOS operations (C) 2010 The Japan Society of Applied Physics

引用

页数：5