Nanosheet FETs and their Potential for Enabling Continued Moore's Law Scaling

被引：11

作者：

Veloso, A. ^{[1
]}

Eneman, G. ^{[1
]}

De Keersgieter, A. ^{[1
]}

Jang, D. ^{[1
]}

Mertens, H. ^{[1
]}

Matagne, P. ^{[1
]}

Litta, E. Dentoni ^{[1
]}

Ryckaert, J. ^{[1
]}

Horiguchi, N. ^{[1
]}

机构：

[1] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

来源：

2021 5TH IEEE ELECTRON DEVICES TECHNOLOGY & MANUFACTURING CONFERENCE (EDTM) | 2021年

关键词：

Nanosheet FETs; Scaling; 3D Device & Circuit Configurations;

D O I：

10.1109/EDTM50988.2021.9420942

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report on nanosheet (NS) FETs as promising candidates to replace finFETs and continue delivering profitable node to node scaling gains. Key fabrication challenges addressed here include device parasitics' reduction via inner spacers integration and channels' stress control. Further scaling options may involve evolution into a forksheet (FS) type of configuration with shrunk p-n spacing, and/or stacking of different polarity devices into a single 3D structure. Lastly, by fully exploring the third dimension, vertical NS (VNS) FETs are also considered for applications such as the selector of ultra-scaled MRAM cells.

引用

页数：3

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