COORDINATING DRAM AND LAST-LEVEL-CACHE POLICIES WITH THE VIRTUAL WRITE QUEUE

被引：3

作者：

Stuecheli, Jeffrey

Kaseridis, Dimitris ^{[1
]}

John, Lizy K. ^{[1
]}

Daly, David

Hunter, Hillery C. ^{[2
]}

机构：

[1] Univ Texas Austin, Dept Elect & Comp Engn, Austin, TX 78712 USA

[2] IBM Thomas J Watson Res Ctr, Exploratory Syst Architecture Dept, Armonk, NY 10504 USA

来源：

IEEE MICRO | 2011年 / 31卷 / 01期

基金：

美国国家科学基金会;

关键词：

cache; cache replacement; cache write-back; DRAM; DRAM page-mode; DRAM parameters; last-level cache; Memory; memory bandwidth; memory scheduling;

D O I：

10.1109/MM.2010.102

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

To alleviate bottlenecks in this era of many-core architectures, the authors propose a virtual write queue to expand the memory controller's scheduling window through visibility of cache behavior. Awareness of the physical main memory layout and a focus on writes can shorten both read and write average latency, reduce memory power consumption, and improve overall system performance.

引用

页码：90 / 98

页数：9

共 34 条

[1] The Virtual Write Queue: Coordinating DRAM and Last-Level Cache Policies
Stuecheli, Jeffrey
Kaseridis, Dimitris
Daly, David
Hunter, Hillery C.
John, Lizy K.
[J]. ISCA 2010: THE 37TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, 2010, : 72 - 82
[2] Efficient STT-RAM Last-Level-Cache Architecture to Replace DRAM Cache
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Menard, Christian
Castrillon, Jeronimo
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[3] The Interaction of Last-Level-Cache Mechanisms on Modern Processors
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[4] Towards Reducing Last-Level-Cache Interference of Co-located Virtual Network Functions
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[5] A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement
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[J]. IEEE ACCESS, 2020, 8 : 59290 - 59304
[7] Rethinking Last-level-cache Write-back Strategy for MLC STT-RAM Main Memory with Asymmetric Write Energy
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[J]. 2019 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED), 2019,
[8] Architecting STT Last-Level-Cache for Performance and Energy Improvement
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[J]. PROCEEDINGS OF THE SEVENTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN ISQED 2016, 2016, : 319 - 324
[9] Cooperatively Managing Dynamic Writeback and Insertion Policies in a Last-level DRAM Cache
Yin, Shouyi
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[J]. 2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2015, : 187 - 192
[10] BlendCache: An Energy and Area Efficient Racetrack Last-Level-Cache Architecture
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[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 41 (12) : 5288 - 5298

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