共 10 条
- [2] Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing 2011 DESIGN, AUTOMATION & TEST IN EUROPE (DATE), 2011, : 449 - 454
- [4] Power-mode-aware buffer synthesis for low-power clock skew minimization IEICE ELECTRONICS EXPRESS, 2016, 13 (14):
- [6] DualSync: Taming Clock Skew Variation for Synchronization in Low-Power Wireless Networks IEEE INFOCOM 2016 - THE 35TH ANNUAL IEEE INTERNATIONAL CONFERENCE ON COMPUTER COMMUNICATIONS, 2016,
- [7] Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing 2018 IEEE 27TH ASIAN TEST SYMPOSIUM (ATS), 2018, : 149 - 154
- [8] A Low-Power Low-Skew Current-Mode Clock Distribution Network in 90nm CMOS Technology 2011 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2011, : 132 - 137
- [9] Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2005, : 1168 - 1171
- [10] Low-power fast-lock delay-recycled clock skew-compensation and/or duty-cycle-correction circuit International Journal of Electrical Engineering, 2012, 19 (02): : 85 - 94