Congestion-aware adaptive routing in 2D mesh multicores

New CMOS processes offer cheaper but less reliable transistors. This trend foreshadows the apparition of processors consisting of hundreds and thousands of cores prone to defects. In this context, the performance of the core interconnect under faults will be critical. In this work, we propose the combination of a novel adaptive routing algorithm and several related router mechanisms, which firstly ensure message transfers under transient and permanent faults and second adapt to congestion in order to improve the interconnect performances. In effect, the widespread 2D mesh topology offers a high redundancy of routes. Hence, a fault-tolerant congestion-aware routing algorithm is able to improve substantially the interconnect efficiency under degraded conditions. Besides, the Virtual Channel allocation is optimized for performance, and a message truncation mechanism is added to cope with dynamic permanent and transient faults.