FPGA IP Obfuscation Using Ring Oscillator Physical Unclonable Function

被引：0

作者：

Hazari, Noor Ahmad ^{[1
]}

Alsulami, Faris ^{[1
]}

Niamat, Mohammed ^{[1
]}

机构：

[1] Univ Toledo, Dept Elect Engn & Comp Sci, 2801 W Bancroft St, Toledo, OH 43606 USA

来源：

NAECON 2018 - IEEE NATIONAL AEROSPACE AND ELECTRONICS CONFERENCE | 2018年

关键词：

FPGA; Hardware Obfuscation; Ring Oscillator; Logic Obfuscation; PUF; IP obfuscation;

D O I：

暂无

中图分类号：

V [航空、航天];

学科分类号：

08 ; 0825 ;

摘要：

IP piracy, reverse engineering, and tampering with FPGA based IP is increasing over time. ROPUF based IP obfuscation can provide a feasible solution. In this paper, a novel approach of FPGA IP obfuscation is implemented using Ring Oscillator based Physical Unclonable Function (ROPUF) and random logic gates. This approach provides a lock and key mechanism as well as authentication of FPGA based designs to protect from security threats. Using the Xilinx ISE design tools and ISCAS 89 benchmarks we have designed a secure FPGA based IP protection scheme with an average of 15% area and 10% of power overhead.

引用

页码：105 / 108

页数：4

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