A Low-Power Hardware Architecture for On-Line Supervised Learning in Multi-Layer Spiking Neural Networks

In this paper, we propose an event-triggered hardware architecture for spiking neural networks with a weight-dependent spike-timing-dependent plasticity (STDP) learning algorithm. Several algorithm adaptations are made on the original learning algorithm in order to reduce the hardware complexity and to improve the energy efficiency of the hardware. In addition, an algorithm-hardware co-design approach is employed to boost the performance. Through leveraging the sparsity of spike trains and local storage units in the network, both the memory requirement of the algorithm and the clock cycles needed per learning iteration are significantly reduced. The proposed hardware architecture is implemented in a 65-nm technology. A three-layer neural network with a configuration of 256-50-10 is demonstrated. The designed chip can conduct inference on a down-sampled MNIST dataset with an energy consumption of 1.12 mu J/ inference while achieving a recognition rate above 90%.