A study of transient thermal spreading of VLSI packaging with multi level scaling

Trend of VLSI chip power consumption sounds switch over from the Moore's law to more moderate curve by the,'' multi core processing '' paradigm. Many of the recent advanced VLSI chips adopt the multiple processing units since clock enhancement is no longer feasible to gain the expected performance based on realistic range of power consumption. Even though, heat flux may keep increasing by further fine semiconductor process and may keep localizing by further complex logics. In this study, thermal impact of hot spot size relative to chip size or the dimension of heat sink is investigated by analytic modeling as well as numerical analysis. The analytic transient thermal spreading model in a solid with transfer function has already proposed and was validated in our previous work. In this study, we have considered the impact of thermal interface between the heat source and conductive and spreading component to the sink. Thermal response in wide rage of scales is discussed from transistor level to a millimeter scale. Each level of such various sizes can be investigated individually and can be built up with some sort of cascade manner. Based on this model, thermal diffusion in silicon substrate, which has the thermal coupling with spreader and thermal interface, will be discussed for a further fine process generation of the chip. The result implies that passive thermal spreading can be achieving to the limit.